A typical metal gate electrode stack comprises an amorphous silicon or polycrystalline silicon capping layer 101, a metal layer 103, and a high K dielectric layer 105, over a semiconductor substrate 107, as illustrated in FIG. 1. For P-type semiconductor devices with metal gate electrodes, the amorphous silicon or polycrystalline silicon layer is typically doped, for example with an appropriate dopant, such as boron (B), aluminum, or gallium, notably B, to improve device performance and control conductivity. However, it was found that during doping, as by ion implantation, a high dopant concentration is formed at the upper surface of the silicon layer which decreases asymptotically downward from the surface leaving a non-uniform dopant concentration profile. The resulting high dopant concentration region 201 near the top surface of silicon layer 101, etches at a rate different from the remainder of silicon layer 101. For example B-doped silicon has a slower etch rate than undoped silicon, and the etch rate changes monotonously with dopant concentration. Accordingly and adverting to FIG. 2, upon etching the layers after dopant implantation, the high B concentration region 201 etches at a significantly lower rate that the remainder of silicon layer 101, resulting in a gate stack having non-linear side surfaces due to undercutting 203, and forming a “shoulder” 205 near the top of the patterned gate. The “shoulder” will not only cause variability in device performance, but also acts as a weak point in subsequent encapsulation, thereby leading to defects.
A need therefore exists for methodology enabling the fabrication of semiconductor devices with metal gate transistors, particularly P-type metal gate transistors, having reduced variability in device performance.